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Mapping an FPGA bitstream format with Claude Code
A developer used Claude Code to map the bitstream format of an Altera Cyclone IV FPGA on an AX301 board. Python fuzzing scripts tested configurations systematically, and results were stored in SQLite. The write-up suggests turning the findings into a formal spec.
Credits
- Post author mm-hacker-news.bsky.social Source ↗
- Repository account 14sea Source ↗
Earliest dated source:
The full story
FPGA makers keep the format of their configuration files (bitstreams) secret, so you have to use their own tools. A developer used Claude Code to start mapping the format for an Altera Cyclone IV chip (EP4CE6F17C8) on a cheap AX301 board. The chip has 6,272 logic elements in 392 blocks.
The method is systematic: Python scripts written by Claude generate thousands of slightly different designs, and Claude compares the resulting bitstreams to find which bits control what. The results go into a SQLite database. The write-up presents this as a reusable template for documenting hardware and suggests turning the findings into a formal specification.
The article reads as a how-to template and is partly garbled, so treat the details with care.
How it was done
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Sources
From the maker's own write-up or code. We summarise what they report; we haven't tested it ourselves.
- DEV / Gentic: how Claude Code reverse engineered an FPGA bitstream
Explains the fuzzing-and-compare workflow and why it suits Claude Code.
- Bluesky: Show HN: Reverse-engineered the FPGA bitstream using Claude Code
https://github.com/14sea/Post author: mm-hacker-news.bsky.socialPosted
- Hacker News: Show HN: Reverse-engineered the FPGA bitstream using Claude CodeRepository account: 14sea